Evaluation and Optimization of Signal Processing Kernels on the TRIPS Architecture
نویسندگان
چکیده
Diminishing performance gains in conventional architectures are driving modern architectures to exploit parallelism more effectively. Next-generation architectures hold promise in the Digital Signal Processing (DSP) arena where high performance and power efficiency are equally important. To better identify optimization techniques on these emerging new architectures, we optimized and evaluated a suite of benchmarks representative of high performance DSP applications. Using these benchmarks, this paper analyzes the performance effects of several code optimizations on a next-generation general purpose processor.
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